h2g2 The Hitchhiker's Guide to the Galaxy: Earth Edition

One reason that nand operations are usually used for examples is that nand gates are very easy to build in an IC process and could be made using early processes.

nand gates are faster than nor gates in nMOS technology - so nand gates were historically used. Nowadays, in cMOS, nor gates are faster.

nand and nor gates are pretty much equally easy to make - but both are easier than and/or gates. and xnor and xor are a right XXXX...

My memory, teaching and job experience don't go as far back as nMOS technology I only ever got to design on CMOS

So was nMOS used in the earliest circuits? The earliest logic circuits were TTL. Were they nMOS? I thought they predated MOS technology.

TTL did come before NMOS and there were other types of logic that can be built with bipolar transistors. Using MOS technology has advantages though (must have or else it wouldn't get used). It's just that it's been a while and I can't remember them right now
Current drain I think is one of them...

just current drain - TTL is switched on or off by current flowing or not flowing, whereas MOS is switched by the presence or abscence of charge.

TTL was faster, but when you half the size of each transistor the energy produced per sq. mm quadruples, so the chips rapidly melted away...

OK. That's what I thought (it's just that Uni is merely a dim and distant memory now and I haven't used any of this stuff since then). So, what that means is that I take a slight issue with the statement "nand gates are faster than nor gates in nMOS technology - so nand gates were historically used."

In fact, it should probably be that NAND gates were easier (don't know about faster) to construct using bipolar technology (now that I think about it, I seem to recall building one from scratch - ahh, transistors, resistors, the heady smell of solder...).

no - faster too...

nand gate, if you recall, have their pull-ups in parallel, and their pull-downs in series. Whereas nor gates have their pull-ups in series, and their pull-downs in parallel.

In nMOS, the pull-downs are transistors, and the pull-ups are passive resistors, so normally it is faster to pull-down than pull-up the output of a gate. But in a nand gate this tendency is reduced because the pull-down circuit is in series, so it has a higher resistance when turned on - this means that pull-up and pull-down times are more balanced, so we can clock the thing at a higher speed.

In cMOS, the same sort of logic makes nor gates better.